Computer bus architectures can only support a limited number of attached nodes. For example, I2C (Inter-Integrated Circuit) buses use a 7-bit address space with 16 reserved addresses. These buses provide a maximum of 112 nodes that communicate on a same bus.
The use of I2C for system devices is reaching a stage where addressing concerns will limit the number of devices on the same bus. Such limitations will cause significant problems for systems requiring a large number of addressable devices.